In many computer systems, components are connected by a shared bus. In such an architecture, only one unit at a time can exert control over the shared bus. Contention among the units which request use of the bus at the same time must be resolved in some manner, i.e., arbitrated.
The most basic arbitration scheme is the so-called "first in first out" arbitration scheme. In this scheme, requests to use the bus are granted strictly in the order in which they arise. This scheme has the advantage of simplicity, but the disadvantage that the relative importance of a device is not taken into account in determining when to grant its request for access to the bus. Thus, devices urgently requiring access to the bus may have to wait while other lower priority devices complete their use of the bus.
A commonly used prior art method for bus arbitration overcomes the above disadvantage by using a central arbiter communicating with all of the devices requesting use of the bus. The central arbiter determines which device has the highest bus use priority taking into account relative importance of the device and how long the device has been waiting to use the bus.
Another known arbitration system can be referred to as "daisy chaining". In this method, a signal indicating that the bus is available for use is transmitted from device to device in priority order. Any device requiring access to the bus captures the signal during its turn and uses the bus. Another prior art scheme offers a rotating priority method wherein bus access is offered to each device in a strict rotation.
The demands for efficient arbitration of bus contentions are especially pronounced in a computer system which processes real time data streams, such as video data streams, and audio data streams, animation data streams. It is crucial for real time data streams to be transferred without interruption since an interruption may be visually or audibly noticeable to an observer. Furthermore, if an arbiter is unable to provide a relatively rapid grant to a device transferring real time data streams, large buffers within the device may be required to store the real time data before it can be transferred. For example, if the arbiter were not assuredly able to provide a relatively swift grant to a video input DMA controller, the video input DMA controller would need large data FIFO buffers to detain high bandwidth video input until it can be transferred via the bus. Large FIFO buffers add significant size and thus cost to the design of a video input controller.
As a result, processing real time data streams requires special control of the system bus beyond what is necessary for non-real time data streams. In some prior art systems, this need is addressed by permitting a real time data stream controller such as a video input DMA controller to retain exclusive use of the bus once granted control until the entire video data stream has been transferred.